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AR# 34553

14.x Timing Analysis - Why is the period requirement different than the period defined in a PERIOD constraint?

Description

I am reviewing the paths analyzed by a PERIOD constraint for a clock in my design.The desired period for this clock is 20 MHz (50 ns).However, the TRCE reports different minimum period requirements for some of the synchronous-to-synchronous paths, for example,25 ns, 8 ns, and so on.

Why are the minimum period requirements different for certain paths in the PERIOD analysis?

Solution

The minimum period requirement might be different than the desired clock period due to the following factors:

  • The source and destination synchronous components are clocked using different edges of the same clock. For example, the source might be clocked by the rising edge, while the destination is clocked by the falling edge. This situation can be observed when the clock arrival times look as follows:
    • Source Clock: sys_clk rising at 0.000ns
    • Destination Clock: sys_clk falling at 13.671ns
  • The source and destination synchronous components are clocked using different clocks. For example, the source might be clocked by one clock, while the destination is clocked by a different clock. The Timing Analysis analyzes the clocks and determines, in time, where these two clocks are closest to each other. This situation can be observed when the clock arrival times look as follows:
    • Source Clock: pll_clk rising at 8.000ns
    • Destination Clock: sys_clk rising at 13.671ns
AR# 34553
Date Created 10/24/2011
Last Updated 12/15/2012
Status Active
Type General Article
Tools
  • ISE Design Suite - 11.1
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  • ISE Design Suite - 13
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