The MIG Virtex-6 DDR2/DDR3 designs are characterized with specific termination schemes and I/O Standards. The DDR2 and DDR3 SDRAM Memory Interface Solution > Core Architecture > Design Guidelines section within the Virtex-6 FPGA Memory Interface User Guide (UG406) includes information on termination guidelines and the MIG design's use of I/O Standards.
NOTE: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
Running SI Simulation using IBIS Models is highly recommended for all memory designs. The user guide section noted above includes information on the following:
Please read the entire section noted above for full details.
The MIG tool creates the UCF using the appropriate standard based on input from the GUI. You can find the MIGUCF in either the "example_design/par" or "user_design/par" directories. Only the I/O standards provided in the MIG UCFs have been tested in hardware during MIG characterization.
6/22/2011 - Added Answer Record 42783
2/17/2011 - Added Answer Record 36104