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AR# 34558

MIG Virtex-6 DDR2/DDR3 - Trace Matching Guidelines


The MIG Virtex-6 DDR2/DDR3 design requires that specific trace matching guidelines be followed to ensure proper behavior in hardware.The trace length/matching guidelines are available in the Virtex-6 Memory Interface Solutions User Guide (UG406); seethe DDR2 and DDR3 Memory Interface Solution -> Design Guidelines -> Trace Lengths section: http://www.xilinx.com/support/documentation/ip_documentation/ug406.pdf

NOTE: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243) The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


Common Trace Matching Questions

Please read the full section noted above for specific details.

  • The trace matching guidelines are established through characterization of high-speed operation. The tight requirements are required for guaranteed operation at maximum performance, but can be relaxed depending on the target bandwidth requirements of the application as shown in the next bullet item.
  • DQ to DQS matching can be relaxed by the change in clock period as the frequency is lowered from the maximum. For example, the maximum supported frequency for the -2 speed grade part is 533 MHz for the center columns. The bit time at this frequency is 937.5 ps. The DQ to DQS PCB skew is allowed to be +/- 5 ps. If this design were operated at 400 MHz, the bit is 1250 ps. The change in period is 1250 - 937.5 = 312.5 ps. Half of this is 156 ps, so the new skew allowed is +/- (156+5) or +/- 161 ps.
  • The package delay should be included when determining the effective trace length.For detailed information, see (Xilinx Answer 34174) as well as the Trace Matching section in UG406 noted above.
  • The provided trace matching guidelines are per memory interface.If a multi-controller design is implemented, the matching is only required across each individual controller.
  • Currently, the design does not include per-pit deskew.Therefore, adherence to the DQ/DQS trace matching is extremely important.
  • DDR3 does not include a trace match guideline between any DQS and CK.This is because the design always performs write leveling which compensates for the skew between DQS and CK and meets the tDQSS specification.
  • DDR2 does include a trace matching guideline between any DQS and CK as write leveling is not performed with DDR2.

Linked Answer Records

Associated Answer Records

AR# 34558
Date Created 05/19/2010
Last Updated 02/05/2013
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
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  • MIG