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AR# 34564

11.5 EDK - Clock_Generator v3.00.a, v3.02.a, Virtex-6 MMCM CLKFBOUT_MULT_F = 2, 3, 4 not valid

Description

Clock Generator v3.00.a

Clock Generator v3.00.a uses a PLL which gets mapped to an MMCM when targeting Virtex-6 devices.

Clock Generator v3.02.a

Certain combinations of the MMCM counter settings, phase shift, and all settings of the variable fine phase shift might cause the CLKOUTn phase shift to show up incorrectly in hardware. This is documented in (Xilinx Answer 33849). This specifically affects Virtex-6 Clock_Generator designs which use a CLKFBOUT_MULT_F value of 2, 3 or 4. Clock_Generator uses the CLKFBOUT_MULT_F parameter to ensure the internal VCO frequency of the MMCM to the highest possible according to the FPGA speed grade. Having a higher VCO frequency reduces jitter on the output clocks. This setting of 2, 3 and 4 will be generated by Clock_Generator in certain combination of high-level parameter settings. For example, the input clock of a Clock_Generator has the following frequencies:

Table 1: CLKFBOUT_MULT_F = 4

FPGA Speed Grade From (MHz) To (MHz)
-1 240 300
-2 288 360
-3 320 400


Table 2: CLKFBOUT_MULT_F = 3

FPGA Speed Grade From (MHz) To (MHz)
-1 300 400
-2 360 480
-3 400 533.3


Table 3: CLKFBOUT_MULT_F = 2

FPGA Speed Grade From (MHz) To (MHz)
-1 400 600
-2 480 720
-3 533.3 800


The ISE 11.4 design tools do not generate an error and issues are seen in hardware. In ISE 11.4.1 design tools, a DRC error is generated.

Solution

Clock Generator v3.00.a

It is highly recommended to use Clock Generator v3.02.a to avoid any issues that an automatic mapping of the PLL to the MMCM can cause.

Clock Generator v3.02.a

To work around this issue, users need to manually modify the MMCM parameters using the Clock_Generator low-level parameters to ensure the CLKFBOUT_MULT_F parameter is not set to 2, 3, and 4 for any of the MMCM, and. meanwhile, the VCO frequency, MMCM parameter values are to remain valid according to the Virtex-6 FPGA Clocking Resources User Guide (UG362). The following work-around steps take CLKFBOUT_MULT_F = 4 as example. The steps also apply to the value of 2 and 3.

Work around steps:

Step 1: Identify if CLKFBOUT_MULT_F = 4 is set to MMCM generated by Clock_Generator

Open the design in XPS, in Clock Generator configuration dialog as shown in Figure 1, check the "Insert low-level parameters in MHS file", and then click OK.

Figure 1. Clock Generator Configuration Dialog's Low-Level Parameter Tab

Open the MHS file and search for the parameter C_MMCMn_CLKFBOUT_MULT_F (n = 0, ..., 3) with in the Clock_Generator instance. If the value equals 4, then manual modification is required; otherwise, no change is required.

Step 2: Manually modify the CLKFBOUT_MULT_F value in MHS file

When manual modification is required, find the following parameter in the Clock_Generator instance:

PARAMETER C_MMCMn_CLKFBOUT_MULT_F = 4.0
PARAMETER C_MMCMn_DIVCLK_DIVIDE = 2
PARAMETER C_MMCMn_CLKOUT0_DIVIDE_F = 2.0
PARAMETER C_MMCMn_CLKOUTm_DIVIDE = 2

Where n = 0, ..., 3 and m = 1, ..., 6. And modify the parameters to ensure the M to D and DO relationship is maintained. For the example, this would be:

PARAMETER C_MMCMn_CLKFBOUT_MULT_F = 8.0
PARAMETER C_MMCMn_DIVCLK_DIVIDE = 4
PARAMETER C_MMCMn_CLKOUT0_DIVIDE_F = 2.0
PARAMETER C_MMCMn_CLKOUTm_DIVIDE = 2

Step 3: Manually modify the C_CLK_GEN value in MHS file

When manual modification is required, find the following parameter in the Clock_Generator instance:

PARAMETER C_CLK_GEN = UPDATE

Either its value is set to "UPDATE", or it is not specified in the MHS file, manually change its value to "PASSED".

PARAMETER C_CLK_GEN = PASSED

This prevents the XPS flow to overwrite the manually modified Clock_Generator low-level parameter values.

DO NOT open Clock_Generator configuration dialog in the XPS any more after manually change the Clock_Generator low-level parameter value. The dialog always overwrites the Clock_Generator low-level parameter values automatically.

AR# 34564
Date Created 03/05/2010
Last Updated 03/15/2010
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
Tools
  • EDK - 11.5
IP
  • Clock Generator