Description
I have a design with bi-directional signals. It simulates successfully when I first run the simulation. However, when I restart the simulation, the simulation fails because the bi-directional signals are not assigned default values as defined in the HDL:
tbio <= TB_INOUT_Z;
where TB_INOUT_Z is defined as a constant via the following HDL
TYPE tb_inout IS
RECORD
inout_sig : STD_LOGIC;
out_sig : STD_LOGIC;
END RECORD;
CONSTANT TB_INOUT_Z : tb_inout :=
(
inout_sig => 'Z',
out_sig => 'Z'
);
How can I resolve this issue?
Solution
This is an issue in ISE Simulator 11. It has been resolved in ISE Design Suite 12.
To download and install the latest version of ISE Design Suite, visit the Download Center at
http://www.xilinx.com/support/download/index.htm