In previous FPGA architectures, MIG included a WASSO (Weighted Average Simultaneously Switching Outputs) Limit field in the Bank Selection screen.
This enabled users to input WASSO limits based on independent calculations through the FPGA WASSO calculators.
The MIG tool for Virtex-6, 7 Series, and UltraScale FPGAs does not include a WASSO Limit.
What is the appropriate MIG flow for analyzing simultaneously switching outputs/noise?
Note: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243).
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The Virtex-6 and 7 Series FPGA families no longer use WASSO or WASSO spreadsheets.
Instead, Simultaneously Switching Noise (SSN) numbers are used and the flow is maintained entirely through the PlanAhead/Vivado tool.
PlanAhead/Vivado tools look at all pins in a bank, determine the input margin available, and then look at how much is lost to SSN.
Because PlanAhead/Vivado now include SSN calculation, MIG no longer includes any type of WASSO or SSN Limit.
The correct flow for Virtex-6, 7 Series, and UltraScale FPGA users interested in SSN analysis is to integrate the MIG output into their user design and go through the PlanAhead/Vivado tool flow.
The SSN predictor assumes that all the I/Os are asynchronous.
However, the memory interface is a synchronous system with phase offsets which reduces the actual SSN.
Additionally, all MIG interfaces are fully validated in hardware, removing SSN concerns within banks containing MIG interfaces.