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AR# 34570

MIG Virtex-6 DDR2/DDR3 - Maximizing Pin allocation in banks


The MIG tool should be used to generate pin-outs for DDR3/DDR2 designs. This ensures that all design rules are followed and the output pin-out is functional in implementation and hardware. There are specific items that have been requested to improve bank packing that are noted in this Answer Record. Some of these items are supported currently through the MIG tool while others users would have to modify at their own risk.

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243) The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


Splitting Address/Control Across Banks

It is possible to split the Address and Control signals across multiple banks. Please adhere to the following:

  • CK/CK# signals should not be moved to an adjacent bank
  • It is recommended that Address and Control only spantwo adjacent banks to minimize skew added across banks. The design does not calibrate for address/control to CK/CK# timing.
  • Signals that are basically static are the best choices to move to an adjacent bank;namely, RESET_N and CKE as these would not have any performance impact.
  • 2T timing signals are better choices to move to an adjacent bank. These are signals that change once everytwo clock cycles and assert a full cycle before needed. 2T signals included address, bank address, RAS_N, CAS_N, and WE_N.
  • CS_N and ODT are "1T" signals and should not be moved to a different bank.
For descriptions of 1T and 2T clocking, refer to Micron technical note TN-47-01.

Removing Signals

It is possible that some signals are not needed by the interface and can be removed.

  • If the design does not required Data Mask, DM may be removed. The MIG tool has an available option to disable DM. Please disable this option rather then making manual modifications to the output MIG rtl and UCF.
  • RESET_N (DDR3 only) and CKE cannot be removed. These signals are required within the memory standard initialization sequences and, therefore, must be connected.
Internal VREF

Internal VREF is a Virtex-6 FPGA feature that allows an internal VREF to be used rather than supplying the source externally. In DDR3/DDR2 designs, two VREF pins are normally required in all banks containing inputs. With Internal VREF, these two pins are not required and the VREF pins within the bank can be used as GPIO. Starting with MIG v3.4, Internal VREF is supported through the MIG GUI.

DCI Cascade

DCI Cascade is a Virtex-6 FPGA feature that allows one bank (the master bank) to have its VRN/VRP pins connected to external reference resistors. Other banks in the same column (slave banks) can use DCI standards with the same impedance as the master bank, without connecting the VRN/VRP pins on these banks to external resistors. For detailed information on this feature, see the DCI Cascading section within The Virtex-6 FPGA Select IO Resources User Guide.

MIG supports usage of DCI Cascade and, by default, enables the option to select the Master Bank when DCI Cascade is used. This allows users to select which bank to dedicate VRN/VRP pins to connect to external resistors. MIG displays all banks in the Master Bank drop-down that satisfy the DCI Cascade Master Bank rules based on the memory interface banks selected. Using DCI Cascade saves two pins in each slave bank.

For more information on using DCI Cascade and setting the Master Bank in MIG, see the DDR2 and DDR3 SDRAM Memory Interface Solution > Getting Started chapter within The Virtex-6 Memory Interface Solutions User Guide.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34308 MIG Virtex-6 DDR3/DDR2 - Verify pin-out/banking requirements are met N/A N/A
AR# 34570
Date Created 05/19/2010
Last Updated 12/15/2012
Status Active
Type General Article
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