This Answer Record applies to the Early Access DVD Release of ISE Design Suite 11.5 ONLY. If you have further questions related to this Early Access Release, please contact Technical Support.
Critical: You must re-run your design through the implementation tools after installing the ISE Design Suite 11.5 DVD.
This Answer Record will become obsolete after the Web Release of ISE Design Suite 11.5, which is scheduled for mid-March 2010. Please refer to the ISE Design Suite 11 - Known Issues for all ongoing issues related to the 11.5 release.
Please note that full hardware validation of IP cores is NOT available for ISE Design Tools 11.5. Current 11.5 IP Known Issues are listed below, but for the latest information on IP Cores after the the Web Release of 11.5, please reference the IP Release Notes Guide and follow the Release Notes Answer Record link for your IP.
11.5 Known Issues:
(Xilinx Answer 33849) Virtex-6 FPGA MMCM - New Requirements for all MMCMs, VCO minimum frequency, and CLKFBOUT_MULT_F values
(Xilinx Answer 32929) Virtex-6 - 11.x Software Known Issues related to the Virtex-6 FPGA
(Xilinx Answer 32651) Spartan-6 - 11.x Software Known Issues related to the Spartan-6 FPGA
(Xilinx Answer 33763) - Virtex-6 FPGA Integrated Block Wrapper v1.4, v1.4 rev 1, and v1.4 rev 2 for PCI Express - Release Notes and Known Issues for ISE Design Suite 11.4 and 11.5
(Xilinx Answer 34611) - Virtex-6 FPGA Integrated Block Wrapper v1.4 rev 2 for PCI Express - Patch to Enable VHDL File Generation for v1.4 rev 2 released in ISE 11.5
(Xilinx Answer 34612) - Virtex-6 FPGA Integrated Endpoint Block v1.4 for PCI Express - Simulation failure when using ISE 11.5 to simulate a v1.4 core generated in ISE Design Suite 11.4
(Xilinx Answer 33277) - Spartan-6 FPGA Integrated Block Wrapper v1.2 and v1.2 rev 1 for PCI Express - Release Notes and Known Issues for ISE Design Suite 11.3, 11.4, and 11.5
(Xilinx Answer 34341) Spartan-6 FPGA Integrated Endpoint Block v1.2 for PCI Express - Simulation failure when using ISE 11.5 to simulate a v1.2 core generated in ISE Design Suite 11.3 or 11.4, in 11.5
(Xilinx Answer 34451) - Spartan-6 FPGA Integrated Endpoint Block v1.2 rev 1 for PCI Express - Simulation never finishes when simulating a v1.2 rev 1 core generated in ISE Design Suite 11.5
(Xilinx Answer 34094) - MIG v3.3, Virtex-6 FPGA DDR2/DDR3 - MMCM CLKFBOUT_MULT_F= 4 not valid, manual modification required
(Xilinx Answer 34099) MPMC v5.04.a - ERROR:LIT:586 - MMCM_ADV symbol "mpmc_core_0/.../u_mmcm_clk_base" has attribute CLKFBOUT_MULT_F set to a value that is outside the valid range of 5 to 64.
(Xilinx Answer 34564) 11.5 EDK - Clock_Generator v3.02.a, Virtex-6 MMCM CLKFBOUT_MULT_F = 2, 3, 4 not valid
(Xilinx Answer 34566) 11.5 EDK - Ethernet Lite core on a SP601 board might not meet timing
(Xilinx Answer 34613) 11.5 EDK - "ERROR:Place:1012 - A clock IOB / DCM component pair have been found that are not place at an optimal clock IOB / DCM site pair"
(Xilinx Answer 34671) LogiCORE IP Display Port v1.1 - Why do I see a simulation with the Display port example design in 11.5?
Please refer to the Release Notes (Xilinx Answer 33313) for details.