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AR# 34574

LogiCORE IP Image Characterization - Release Notes and Known Issues

Description

This answer record contains the Release Notes and Known Issues list for the CORE Generator software and LogiCORE IP Image Characterization Core.

The following information is listed for each version of the core:
  • New Features 
  • Bug Fixes 
  • Known Issues 
LogiCORE IP Image Characterization Lounge:
http://www.xilinx.com/products/ipcenter/EF-DI-IMG-CHAR.htm

Note: Not recommended for new designs. The core is removed from IP catalog as of 2014.1. Please contact Xylon, our IP partner, for solutions related to image characterization.

Solution

General LogiCORE IP Image Characterization Issues

LogiCORE IP Image Characterization v3.00.a
  • Initial release in ISE Design Suite 14.4, Vivado 2012.4
Supported Devices (ISE)
  • All 7 Series devices
  • All Virtex-6 devices
  • All Spartan-6 devices
Supported Devices (Vivado)
  • All 7 Series devices

New Features

  • Added optional Input Chroma Filter
  • Added AXI4 Stream Interfaces to AXI DataMover, replacing AXI4 Memory Map Interface
  • Updated to standard video address map
  • Added AXI4-Lite Clock Domain 
Resolved Issues (ISE)
  • Fixed Memory Collisions Errors in netlist simulations. 
Resolved Issues (Vivado) 
  • Fixed Memory Collisions Errors in netlist simulations. 
Known Issues (ISE)
  • N/A
Known Issues (Vivado)
  • N/A


LogiCORE IP Image Characterization v2.0

  • Initial release in ISE Design Suite 13.3

Supported Devices

  • Virtex-7
  • Virtex-7 XT (7vx485t)
  • Virtex-7 -2L
  • Kintex-7
  • Kintex-7 -2
  • Virtex-6 XC CXT/LXT/SXT/HXT
  • Virtex-6 XQ LXT/SXT
  • Virtex-6 -1L XC LXT/SXT
  • Spartan-6 XC LX/LXT
  • Spartan-6 XA
  • Spartan-6 XQ LX/LXT
  • Spartan-6 -1L XC LX

New Features

  • Added AXI4 Stream Input  
  • Added AXI4 Memory Map Interface   
  • Added AXI4 Lite Interface to the pCore for register accesses
  • ISE 13.3 software support

Bug Fixes

Known Issues

  • N/A

LogiCORE IP Image Characterization v1.1
There was a v1.1 rev1 patch available in (Xilinx Answer 38243). This patch was intended to fix issues listed below as (Xilinx Answer 38527), (Xilinx Answer 38529).

- Initial Release in ISE Design Suite 12.3

New Features
  • Programmable register control
  • Option to remove the following to save resources:
    • Y Means and Variances
    • U Means and Variances
    • V Means and Variances
    • Motion Means and Variances
    • Frequency (Low and High) Means and Variances
    • Edge Means and Variances
    • Saturation Means and Variances
    • Y Histograms
    • U Histograms
    • V Histograms
    • Hue Histograms
  • Option to select the number of Color Selects
  • ISE 12.3 software support

Bug Fixes
  • (Xilinx Answer 35641) Why is the control register in big endian format, instead of little endian format as documented in the data sheet when targeting Spartan-6 or Virtex-6 FPGA?
Known Issues

LogiCORE IP Image Characterization v1.0

  • Initial release in ISE Design Suite 12.1

New Features

  • Programmable register control
  • Selectable processor interface
    • EDK pCore
    • General Purpose Processor
  • Global and Block Means and Variances for:
    • Luminance / Chrominance Content
    • Edge Content
    • Motion Content
    • Color Content
  • Global Histograms for:
    • Luminance
    • Chrominance
    • Hue
  • Support for 8-bit, YUV 4:2:2 or YUV 4:2:0 data
  • Support for 8-bit Motion data
  • Support for image sizes up to 1920x1080p @30fps or 1280x720 @ 60fps
  • Support for Virtex-6, Spartan-6, Virtex-5 and Spartan-3A DSP FPGAs
  • ISE 12.1 software support
  • Programmable register control
Bug Fixes
  • N/A
Known Issues
  • (Xilinx Answer 35641) Why is the control register in big endian format, instead of little endian format as documented in the data sheet when targeting Spartan-6 or Virtex-6 FPGA?

Linked Answer Records

Child Answer Records

Associated Answer Records

AR# 34574
Date Created 04/26/2010
Last Updated 04/29/2014
Status Active
Type Release Notes
IP
  • Image Characterization