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AR# 34577

11.x ISE Simulator (ISim) - Unable to observe output at output buffers

Description


When I perform a timing simulation on my design, some of the output data gets "dropped" or swallowed. This seems to happen at particular clock frequencies. If I slow down the clock, my timing simulations run successfully.However, when using the desired clock frequency, no timing violations are observed in Timing Analyzer, or in the simulator.

What would cause my output logic to be "dropped" or "swallowed"?

Solution


A pulse on an input pin of a component might be swallowed or dropped if the period of the pulse is shorter than the delay ofthecomponent. For example, a pulse of 1 ns through an IBUFDS with a component delay of 1.2 ns might not appear at the output of the buffer.

To address this issue, run the following ISim Tcl command before running (or after restarting) the simulation:

specify pathpulse .001

This issue has been resolved in ISE Design Suite 12.1.

To download and install the latest version of ISE Design Suite, visit the Download Center at http://www.xilinx.com/support/download/index.htm
AR# 34577
Date Created 03/04/2010
Last Updated 12/15/2012
Status Active
Type General Article
Tools
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
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  • ISE Design Suite - 11.5
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