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AR# 34581 11.x ChipScope Pro - BUFG insertion is always enabled on the JTAG clock for the ICON core

When generating a ChipScope ICON Core through the CORE Generator Inserter or PlanAhead flows, a BUFG is always inserted on the JTAG clock line. This occurs regardless of the GUI or "Enable_Jtag_Bufg" attribute settings.

This is the case from 11.x forward. BUFG insertion is forced. Due to the increasing speed and complexity of devices and associated designs, a BUFG on the JTAG clock is necessary to ensure that the ChipScope cores are identified by the Analyzer. The BUFG needs to be used to avoid skew on the JTAG clock; if not present, corruption of sampled data and issues with core detection will occur.

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AR# 34581
Date Created	05/05/2010
Last Updated	12/15/2012
Status	Active
Type	General Article
Devices	Spartan-3 Spartan-3 XA Spartan-3A More Spartan-3A DSP Spartan-3AN Spartan-3E Spartan-6 LX Spartan-6 LXT Spartan-II Spartan-IIE Spartan-IIE XA Spartan-XL IQ System ACE Virtex Virtex QPro/R Virtex-4 FX Virtex-4 LX Virtex-4 QPro/R Virtex-4 SX Virtex-5 FXT Virtex-5 LX Virtex-5 LXT Virtex-5 SXT Virtex-5 TXT Virtex-5Q Virtex-6 CXT Virtex-6 HXT Virtex-6 LX Virtex-6 LXT Virtex-6 SXT Virtex-E Virtex-E QPro Virtex-EM Virtex-II Virtex-II Pro Virtex-II Pro X Virtex-II QPro/R Less
Tools	ChipScope Pro - 11.1 ChipScope Pro - 11.2 ISE Design Suite - 11.1 More ISE Design Suite - 11.2 ISE Design Suite - 11.3 ISE Design Suite - 11.4 PlanAhead - 11.1 PlanAhead - 11.2 Less
IP	ChipScope ICON ChipScope ILA ChipScope OPB IBA More ChipScope PLB IBA ChipScope PLBv46 IBA ChipScope VIO Less

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