UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 34587

MIG v3.4 - Release Notes and Known Issues for ISE Design Suite 12.1

Description

This Release Notes and Known Issues Answer Record is for the Memory Interface Generator (MIG) v3.4 released in ISE Design Suite 12.1 and contains the following information:
 
  • General Information
  • Software Requirements
  • New Features
  • Resolved Issues
  • Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Solution


General Information

MIG v3.4 is available through ISE Design Suite 12.1.

For a list of supported memory interfaces and frequencies for Spartan-3 Generation, Virtex-4, and Virtex-5 FPGA, see the MIG User Guide:
http://www.xilinx.com/support/documentation/ip_documentation/ug086.pdf

For a list of supported memory interfaces and frequencies for the Spartan-6 FPGA MCB, see the Spartan-6 FPGA Memory Controller User Guide:
http://www.xilinx.com/support/documentation/user_guides/ug388.pdf

For a list of supported memory interfaces and frequencies for Virtex-6 FPGA, see the Virtex-6 FPGA Memory Interface Solutions User Guide:
http://www.xilinx.com/support/documentation/ip_documentation/ug406.pdf


Software Requirements
  • Xilinx ISE Design Suite 12.1
  • Synplify Pro C-2009.12 Support
  • 32-bit Windows XP
  • 32-bit Linux Red Hat Enterprise 4.0
  • 64-bit/32-bit Linux Red Hat Enterprise 4.0
  • 64-bit XP professional
  • 32-bit Vista business
  • 64-bit SUSE 10
  • 64-bit/32-bit Linux Red Hat Enterprise 5.0 support
  • 64-bit Windows Vista support
  • 32-bit SUSE 10 support

New Features




  • ISE Design Suite 12.1 software support
  • Verify UCF and Update Design support for Virtex-6 FPGA designs
  • Pin Selection support for Virtex-6 FPGA designs
  • Support of Default Bank Selections for Virtex-6 FPGA Multi controller designs
  • Support of Automotive Spartan-6 FPGA parts
  • Dual rank parts support for Virtex-6 FPGA DDR2 and DDR3 SDRAM





Resolved Issues

MIG Tool
  • Removed the scroll bars from controller options pages in MIG
    • CR 471763
  • Elaborated the text in the PCB GUI page
    • CR 536419
  • MIG v3.3: Tool should indicate it is not possible to place Address/Control and data for 8-bit interface in 1 bank
    • CR 536626
  • Included the usage of VRN/VRP and VREF pins in the data sheet of MIG designs
    • CR 538474
  • Modified the functionality of providing the Design Notes through the XML instead of doc format. All of the special characters are removed
    • CR 538714
    • CR 538715
  • Added the Support for Dual Rank parts for Virtex-6 designs
    • CR 539063
  • Removed the Static Calibration Memory Address option in the FPGA options page
    • CR 542432
  • Grayed out tuned input termination option for the LPDDR design in the FPGA Option page
    • CR 542438
  • Applied the appropriate standard in the UCF according to the memory part supported
    • CR 543157
  • Reflected the parameter value mcb1_MEM_MDDR_ODS with the drive strength value selected in GUI
    • CR 544691
  • Added the option to select Three-Quarter Strength and removed the One-eighth option in Drive Strength Selection
    • CR 545582
  • Modified the range of tREFI parameter selection for 5 - 10.5 us to 1 - 10.2 us
    • CR 547263
  • Corrected the CLKFBOUT_MULT_F value to be always greater than 4
    • CR 551677
Virtex-6 FPGA
  • MIG violates CKE JEDEC requirement when memory initialization sequence is not skipped in simulation.
    • CR 548510
  • MIG v3.3-Virtex-6 - Request to have TZQI parameter in the top level
    • CR 541639
  • VCO frequency equation in infrastructure.v is incorrect.
    • CR 541611

Virtex-5 FPGA
  • ISE10.1.03 xc5vtx240t-ff1759 MIG 2.3 DDR2 SDRAM not meeting timing constraints at 300 MHz for 144-bit controller
    • CR 546948
  • Write_data_timing spreadsheet should include PLL Tstaphaoffset in both before and after DQS columns
    • CR 538026
  • MIG, Virtex-5, QDRII -The frequency limitation is inconsistent with QDRII Data Sheet
    • CR 545688
Spartan-6 FPGA
  • Request to add comment in UCF for CONFIG VCCAUX=2.5; constraint
    • CR 543583
  • MIG 3.2 - MCB PLLLOCK pin fails timing in Spartan-6 FPGA designs
    • CR 539481
  • MIG 3.2 - Add support for Auto Refresh at industrial temp in Spartan-6 FPGA
    • CR 538514
Spartan 3 FPGA
  • MIG DDR2 Design does not meet timing
    • CR 531350

Known Issues

Virtex-6 FPGA DDR2/DDR3
(Xilinx Answer 35252) MIG v3.0-3.3 Virtex-6 DDR3 - REFCLK Frequency must be 300 MHz for interfaces running between 480-533 MHz

(Xilinx Answer 35742) MIG v3.0-3.4 Virtex-6 DDR2 SDRAM - Incorrect timing on DDR2_RAS_N 
(Xilinx Answer 36195) MIG v3.4 Virtex-6 DDR2 - Unroute errors occur on dqs_p_iodelay due to Map option

Virtex-6 FPGA QDRII+ SRAM
(Xilinx Answer 33289) MIG v3.1, v3.2, v3.3, v3.4 Virtex-6 FPGA QDRII+ - Changes required to Samsung simulation model for proper operation and completion of calibration

Spartan-6 FPGA MCB
(Xilinx Answer 35978) MIG Spartan-6 MCB - Last word of read burst fails in hardware - bitstream update required for all MCB designs
(Xilinx Answer 35976) MIG Spartan-6 MCB - Design does not come out of reset and requires power-cycle to regain functionality - SW / IP update required
(Xilinx Answer 35818) Spartan-6 FPGA - Memory Controller Block (MCB) Performance Change for DDR2 and DDR3 interfaces
(Xilinx Answer 35044) 11.5/12.1 Spartan-6 Place - The clock placer is not accounting for the proper PLL_ADV to BUFFPLL_MCB connection in larger devices - Results in MIG/MPMC MCB Calibration Failures in Hardware
(Xilinx Answer 35499)
MIG v3.4 Spartan-6 Traffic Generator - 128-bit Bi-Directional Port Example Design does not work in hardware
(Xilinx Answer 35250) MIG Spartan-6 MCB - MIG generated ise_flow.bat script file produces error during XST on Windows
(Xilinx Answer 35238) MIG v3.4 Spartan-6 MCB LPDDR - MIG generated ise_flow.bat script file is missing BitGen command to create a bit file
(Xilinx Answer 35245) MIG Spartan-6 MCB - User Interface cannot send commands until calibration completes (cal_done asserts)
(Xilinx Answer 34055) MIG Spartan-6 FPGA MCB - What are the requirements for the RZQ and ZIO pins?
(Xilinx Answer 34089) MIG Spartan-6 FPGA MCB - Some bits of the MCB address bus (mcbx_dram_addr) may violate the input hold time (tIH) specification of the memory device
(Xilinx Answer 34046) MIG v3.3/v3.4, Spartan-6 LPDDR - Calibrated and Un-Calibrated Input Termination features not supported
(Xilinx Answer 35289) MIG v3.4, Spartan-6 FPGA LPDDR - When running the LPDDR design the traffic generator stops sending commands after long write bursts.
(Xilinx Answer 35290) MIG v3.4, Spartan-6L - Error when using Synplify Pro as a synthesis tool and targeting low power Spartan-6 devices
(Xilinx Answer 35485) MIG Spartan-6 - DDR2 - When using Synplify Pro for synthesis the design fails to send data in hardware.
(Xilinx Answer 35057) MIG v3.4, v3.4 - Spartan-6 - The MCB appears to violate the DDR2 Initialization Sequence

(Xilinx Answer 35869) MIG v3.4 - Spartan-6 - When simulating the example design with ModelSim PE I get an "Iteration limit" error.

Virtex-5 FPGA Designs
(Xilinx Answer 35248) MIG v3.4 Virtex-5 FPGA - All VHDL Example Design outputs using Synplify flow will fail in hardware

(Xilinx Answer 36335) MIG v3.3, v3.4 Virtex-5 DDR2 - Data corruption occurs at the beginning or end of a read burst

Virtex-4 FPGA Designs
(Xilinx Answer 35291) MIG v3.4 - Virtex-4 - RLDRAMII - During simulation of the VHDL design iteration limit error occurs

MIG Tool
(Xilinx Answer 35247) MIG v3.4 Virtex-6 DDR2/DDR3 - Fixed Pin-Out tool does not allow selection of VREF sites

Linked Answer Records

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
35742 MIG v3.0-3.4 Virtex-6 DDR2 SDRAM - Incorrect timing on DDR2_RAS_N N/A N/A
35499 MIG v3.4 Spartan-6 Traffic Generator - 128-bit Bi-Directional Port Example Design does not work in hardware N/A N/A
35485 MIG Spartan-6 DDR2 - When I use Synplify Pro for synthesis the design fails to send data in hardware N/A N/A
35291 MIG v3.4 - Virtex-4 - RLDRAMII - During simulation of the VHDL design iteration limit error occurs N/A N/A
35290 MIG v3.4, Spartan-6L - Error when using Synplify Pro as a synthesis tool and targeting low power Spartan-6 devices N/A N/A
35289 MIG v3.4, Spartan-6 FPGA LPDDR - When running the LPDDR design the traffic generator stops sending commands after long write bursts N/A N/A
35252 MIG v3.0-3.4 Virtex-6 DDR3 - REFCLK Frequency (IODELAYCTRL Reference clock) must be 300 MHz for interfaces running between 480-533 MHz N/A N/A
35250 MIG Spartan-6 MCB - MIG generated ise_flow.bat script file produces error during XST on Windows N/A N/A
35248 MIG v3.4 Virtex-5 FPGA - All VHDL Example Design outputs using Synplify flow will fail in hardware N/A N/A
35247 MIG v3.4 Virtex-6 DDR2/DDR3 - Fixed Pin-Out tool does not allow selection of VREF sites N/A N/A
35245 MIG Spartan-6 MCB - User Interface cannot send commands until calibration completes (cal_done asserts) N/A N/A
35238 MIG v3.4 Spartan-6 MCB LPDDR - MIG generated ise_flow.bat script file is missing the Bitgen command to create a bitfile N/A N/A
34089 MIG Spartan-6 FPGA MCB - In ES Devices, some bits of the MCB address bus (mcbx_dram_addr) might violate the input hold time (tIH) specification of the memory device N/A N/A
34055 MIG Spartan-6 FPGA MCB - What are the requirements for the RZQ and ZIO pins? N/A N/A
34046 MIG v3.3-v3.5, Spartan-6 LPDDR - Calibrated and Un-Calibrated Input Termination features not supported N/A N/A
33289 MIG v3.1, v3.2, v3.3, v3.4 Virtex-6 FPGA QDRII+ - Changes required to Samsung simulation model for proper operation and completion of calibration N/A N/A
35978 Design Advisory for MIG, MPMC Spartan-6 MCB - Last word of read burst fails in hardware - bitstream update required for all MCB designs N/A N/A
35603 MIG Virtex6 QDRII+ - Does MIG support x9 QDRII+ devices? N/A N/A
36195 MIG v3.4 Virtex-6 DDR2 - Unroute errors occur on dqs_p_iodelay due to Map option N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
35485 MIG Spartan-6 DDR2 - When I use Synplify Pro for synthesis the design fails to send data in hardware N/A N/A
35291 MIG v3.4 - Virtex-4 - RLDRAMII - During simulation of the VHDL design iteration limit error occurs N/A N/A
35290 MIG v3.4, Spartan-6L - Error when using Synplify Pro as a synthesis tool and targeting low power Spartan-6 devices N/A N/A
35289 MIG v3.4, Spartan-6 FPGA LPDDR - When running the LPDDR design the traffic generator stops sending commands after long write bursts N/A N/A
35250 MIG Spartan-6 MCB - MIG generated ise_flow.bat script file produces error during XST on Windows N/A N/A
35248 MIG v3.4 Virtex-5 FPGA - All VHDL Example Design outputs using Synplify flow will fail in hardware N/A N/A
35247 MIG v3.4 Virtex-6 DDR2/DDR3 - Fixed Pin-Out tool does not allow selection of VREF sites N/A N/A
35245 MIG Spartan-6 MCB - User Interface cannot send commands until calibration completes (cal_done asserts) N/A N/A
35238 MIG v3.4 Spartan-6 MCB LPDDR - MIG generated ise_flow.bat script file is missing the Bitgen command to create a bitfile N/A N/A
34046 MIG v3.3-v3.5, Spartan-6 LPDDR - Calibrated and Un-Calibrated Input Termination features not supported N/A N/A
33289 MIG v3.1, v3.2, v3.3, v3.4 Virtex-6 FPGA QDRII+ - Changes required to Samsung simulation model for proper operation and completion of calibration N/A N/A
35252 MIG v3.0-3.4 Virtex-6 DDR3 - REFCLK Frequency (IODELAYCTRL Reference clock) must be 300 MHz for interfaces running between 480-533 MHz N/A N/A
AR# 34587
Date Created 04/30/2010
Last Updated 09/03/2014
Status Active
Type Release Notes
IP
  • MIG