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AR# 34588

MIG Virtex-6 DDR2/DDR3 - Board Debug including general debug, calibration debug, and data error debug


Determining a root cause for a hardware issue can be a time consuming process.

With memory interface designs, general board layout, adherence to MIG layout, pin-out, and banking rules, and extreme care in SI simulation using IBIS models are key steps in ensuring proper behavior in hardware.

Please go back to the Hardware (Xilinx Answer 34286) section of this MIG Virtex-6 Design Assistant for information on these check points.

Once these items have been verified, this answer record should serve as a starting point for debugging calibration failures, data errors, and general board level issues.

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243).

The Xilinx MIG Solution Center is available to address all questions related to MIG.

Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


Before investigating calibration failures or data errors, you should go through the General Board Level Debug section of this Design Assistant to ensure a functional board and layout.

General Board Level Debug

Once the board layout is verified, the next step in hardware debug is to load the provided MIG Example Design with the Debug Port enabled on the board.

The Debug Port includes critical debug signals brought up through ChipScope modules that are used in this debug flow. 

To enable the Debug Port, generate your MIG design and Enable the Debug Signals for Memory Controller on the FPGA Options GUI screen.

For more information on the debug port, see (Xilinx Answer 35206).


The Example Design is a known working design with a fully operational Traffic Generator.

The Traffic Generator sends out write commands, reads back the data, and performs a comparison to ensure a working system. 

The Traffic Generator can be configured to send many different types of data patterns to test for different board related issues such as SSO and Cross-Talk.

For information on the Traffic Generator and its patterns, please see the DDR2/DDR3 SDRAM Memory Interface Solution > Getting Started section of (UG406).

Once the Example Design is running in your hardware, there are a few simple checks to determine the high level failure occurring.

Monitor the phy_init_done and error flags to determine if a calibration or bit/data error has occurred:


Initial Checks:
Are the clocks toggling?
- Check is the MMCM locked (pll_lock in infrastructure.v)
- Check if IODELAY Control Ready goes high (iodelay_ctrl_rdy in example_top.v)
- Verify input PCB clock sources and output CK/CK# using oscilloscope

Check the reset polarity of the design
- Check the RST_ACT_LOW parameter value is correct

Debugging Calibration Failures - (Xilinx Answer 34743)

Debugging Data Errors - (Xilinx Answer 34709)

    Linked Answer Records

    Associated Answer Records

    AR# 34588
    Date Created 05/18/2010
    Last Updated 12/19/2014
    Status Active
    Type General Article
    • Virtex-6 CXT
    • Virtex-6 HXT
    • Virtex-6 LX
    • More
    • Virtex-6 LXT
    • Virtex-6 SXT
    • Less
    • MIG