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Virtex-6 FPGA Integrated Block Wrapper v1.4 rev2 for PCI Express - Patch to Enable VHDL File Generation for v1.4 rev 2 released in ISE 11.5

AR# 34611

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Topic PCIe
Last Updated 03/05/2010
Status Active
Description

The Virtex-6 FPGA Integrated Block Wrapper v1.4 rev 2 for PCI Express was released as part of the ISE 11.5 update. For more information on ISE 11.5, see (Xilinx Answer 34571). The Virtex-6 FPGA Integrated Block Wrapper was updated in 11.5 to fix the issue discussed in (Xilinx Answer 34144). Users who generate the core in 11.5 will receive v1.4 rev2 and do not need to worry about the issue with the MMCM VCO settings discussed in (Xilinx Answer 34144).

However, users who update to ISE 11.5 and want to use VHDL should download the v1.4 rev 3 patch. This patch enables VHDL generation of the user example design and the simulation testbench.

Solution

Please see (Xilinx Answer 34279) to download this patch.

Revision History

03/08/2010 - Initial Release

Applies To

Devices

  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT

IP

  • Virtex-6 FPGA Integrated Endpoint Block for PCI Express
 
 
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