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AR# 34612 Virtex-6 FPGA Integrated Endpoint Block v1.4 for PCI Express : Simulation failure when using ISE 11.5 to simulate a v1.4 core generated in ISE Design Suite 11.4

Description

When usingISE 11.5 to simulate a v1.4 wrapper generated in ISE 11.4, simulation will fail with the following error message:

Attribute Syntax Error : The calculation of VCO frequency=500.000000 Mhz. This exceeds the permitted VCO frequency range of 600.000000 Mhz to 1600.000000 Mhz. The VCO frequency is calculated with formula: VCO frequency = CLKFBOUT_MULT_F / (DIVCLK_DIVIDE * CLKIN1_PERIOD). Please adjust the attributes to the permitted VCO frequency range.

Solution

Xilinx recommends regenerating the core using ISE 11.5. This will generate v1.4 rev 2 of the core in which this problem will be fixed.

Revision History

03/08/2010 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
33763 Virtex-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - Release Notes and Known Issues for ISE Design Suite 11.4 and 11.5 N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
33763 Virtex-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - Release Notes and Known Issues for ISE Design Suite 11.4 and 11.5 N/A N/A

Actions

AR# 34612
Date Created 03/05/2010
Last Updated 05/22/2012
Status Active
Type Known Issues
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
IP
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
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