The values forthe ML510 DDR2 are as follows:
- C_DDR_DWIDTH = 64
- Address Offset = log2(64/8) = 3
- Column Address Width = 10
- Row Address Width = 14
- Bank Address Width = 2
Going through the "Row Conflict and Bank Conflict Mask Settings" on page 13 of the
LogiCORE IP DDR2 Memory Controller for PowerPC 440 Processors (v3.00b) Data Sheet -v1.9, April 19, 2010 (DS567):
the MI_BANKCONFLICT_MASK = 32'h01800000 and
the MI_ROWCONFLICT_MASK = 32'h007FFE00 for the ML510 board.
This problem has been fixed in the 12.2 release.