We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 34617

Spartan-6 Phase Detector usage


There can be problems with the Spartan-6 FPGA phase detector control signals in some situations. There is a simple workaround that is described in this article that will be published in the next version of the User's Guide.


To ensure proper operation of phase detector the INC signals to the delays should only be asserted high simultaneously with the CE signals and should kept low at all other times when in phase detector mode. Refer to figure 3-4 in the Spartan-6 FPGA SelectIO User's Guide.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
46791 Spartan-6 FPGA Design Assistant - Troubleshoot Common Fabric Problems N/A N/A
AR# 34617
Date Created 03/09/2010
Last Updated 12/15/2012
Status Active
Type General Article
  • Spartan-6 LX
  • Spartan-6 LXT