loadless signals in this design. This design will cause Bitgen to issue DRC warnings"">
The following message occurs when PAR's DRC check detects that there are signals in the design with a valid driver, but no downstream load(s).
"PAR - WARNING:PAR:283 - There are < number > loadless signals in this design. This design will cause Bitgen to issue DRC warnings."
This message can occur when PAR has trimmed a downstream load due to logic consolidation and a KEEP or Sconstraint on the net has prevented that net from being trimmed.
This message can occur when there are multiple levels of hierarchy in the design and the MAP tool is unable to properly resolve connectivity of a net across the hierarchical boundary. Try re-running through MAP and PAR with the -ignore_keep_hierarchy option set in MAP.
This message can occur when a ChipScope Pro analyzer core is inserted into a design and interferes with the connectivity. Attempt to remove the ChipScope Pro analyzer core temporarily to see if this resolves the issue. If so, please file a WebCase with Xilinx Technical Support: