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AR# 34650

Virtex-6 FPGA Connectivity Kit TRD - Timing Issues


Is it possible to run the TRD again after making alterations to the design and meet timing?


It is difficult to meet timing on -1 parts of the silicon with the current version of the tools. Xilinx will make sure that bit/mcs files sent out with this TRD will meet timing. If users change parts of the design, then the user might need to run cost tables or floorplan the design to ensure that the design meets timing.
AR# 34650
Date Created 04/09/2010
Last Updated 04/09/2010
Status Active
Type General Article