The output registers of the Block Ram may not initialize to the proper value immediately after configuration.
In ISE Design Suite 11.5 and earlier software versions, there is an issue that affects the output registers of the Block RAM. The Block RAM output registers/latches will be initialized after configuration to the Set/Reset value (SRVAL_A or SRVAL_B) instead of the intended Initialization value (INIT_A or INIT_B).
This issue will only affect a design which meets the two following criteria:
- The INIT value for the output register of the Block RAM is different than the SR value. The default for both the INIT value and the SRVAL value is zero ('0').
- The INIT value of that output register is required to be a certain value for the design. After the first clock cycle, the register will be updated to the new value, so it will most likely not be an issue.
There are options for a workaround. Any of the following can be done:
- Wait until ISE 12.1, which will have the issue fixed.
- Add the STARTUP_SPARTAN6 design primitive to your design. After configuration, assert a GSR, which will properly set the INIT value to all Block RAM output registers.
- Make adjustments to the design to ignore the initial value of the output register, or match the INIT value to the SRVAL value.
This issue will be fixed in the ISE Design Suite 12.1 Software.