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AR# 34660

11.4 EDK, MPMC v5.04.a - ERROR:HDLCompiler:432 - Formal has no actual or default value


When using MPMC in Virtex-6 or Spartan-6 FPGA with a PLB, SDMA, or VFBC PIM, an error similar to the following occurs:

ERROR:HDLCompiler:432 - "EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v6_00_a/hdl/vhdl/plbv46_pim_wrapper.vhd" Line 82: Formal <c_mpmc_pim_baseaddr> has no actual or default value.
ERROR:HDLCompiler:559 - "EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v6_00_a/hdl/verilog/mpmc.v" Line 4578: Could not find module/primitive <plbv46_pim_wrapper>.
ERROR:EDK:546 - Aborting XST flow execution!

The MPMC synthesis report may show the following warnings

WARNING:HDLCompiler:874 - "EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v6_00_a/hdl/verilog/mpmc.v" Line 4578: Value -2147483648 is out of target constraint range -2147483647 to 2147483647

How do I resolve this issue?


Currently, the only workaround is to not allow a PLB/SDMA/VFBC PIM to havean address rangecontaining 0x80000000 or higher in Virtex-6 or Spartan-6 FPGA.

This issue is currently planned to be fixed in ISE 12.1.

AR# 34660
Date Created 03/15/2010
Last Updated 12/15/2012
Status Active
Type General Article
  • Spartan-6 LX
  • Spartan-6 LXT
  • EDK - 11.4
  • EDK - 11.5
  • Multi-Port Memory Controller (MPMC)