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AR# 34671

LogiCORE IP Display Port v1.1 - Why do I see a simulation error with the Display port example design in 11.5?

Description

Why do I see a simulation error with the Display port example design11.5?

In simulation of the Source core, the following error occurs:

# do simulate_mti.do
# work
# Compiling Display Port Simulation Core
# Compiling Display Port Example Design
# Compiling Display Port Testbench
# vsim -L unisims_ver -L XilinxCoreLib_ver -L secureip -voptargs=\"+acc\" work.glbl work.displayport_v1_1_tb
# ** Note: (vsim-3812) Design is being optimized...
# ** Error: C:/Xilinx/11.1/ISE/verilog/src/unisims/PLL_ADV.v(1102): Failed to find 'PLL_LOCKG' in hierarchical name.
# Optimization failed
# Error loading design
Error loading design

Solution

This issue has been resolved in the Display Port v1.2 in Xilinx ISE Design Suite 12.1.

To work around this problem, perform the following:

  1. Delete the "glbl.v" file in the simulation/ directory.
  2. Update the "simulation_mti.do" file.
  3. Delete "vlog -quiet -work $work ../glbl.v"
  4. Add "vlog -quiet -work $work$XILINX/verilog/src/glbl.v"
  5. NOTE: Make sure to replace $XILINX with your Xilinx Software Install location.

For a detailed list of LogiCORE IP Display Port Release Notes and Known Issues, see (Xilinx Answer 33258).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
33258 LogiCORE IP DisplayPort - Release Notes and Known Issues N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
33258 LogiCORE IP DisplayPort - Release Notes and Known Issues N/A N/A
AR# 34671
Date Created 03/09/2010
Last Updated 12/15/2012
Status Active
Type General Article
IP
  • DisplayPort