11.x/12.x ChipScope, IBERT - Virtex-6 GTX, CORE Generator does not list upper GTXE1 quads of SX475T and LX550T
Description
The upper GTXE1 quads 116, 117, and 118 of the SX475T and LX550T devices are not available in the CORE Generator interface when I attempt to generate an IBERT design.
How do I work around this issue?
Solution
In ChipScope 12.2, the upper quads are available for selection, but the core is not implemented correctly and the reference clock is not connected. This issue is resolved in ChipScope 12.3. An assisted work-around is available in 12.1 and 12.2.
If you require further assistance, open a WebCase with Xilinx Support at:
http://www.xilinx.com/support/clearexpress/websupport.htm
Applies To
Devices
- Virtex-6 SXT
- Virtex-6 LXT
Design Tools
- ISE Design Suite - 11.5
- ISE Design Suite - 11.1
- ISE Design Suite - 11.2
- ISE Design Suite - 11.3
- ISE Design Suite - 11.4