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AR# 34677

MIG Virtex-6 and 7 Series DDR2/DDR3 User Interface - Performing Writes


This part of the MIG Design Assistant will guide you to information on performing writes to the User Interface.

NOTE: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243) 

The Xilinx MIG Solution Center is available to address all questions related to MIG. 

Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


Driving Write on the User Interface

The write data is registered in the write FIFO when app_wdf_wren is asserted and app_wdf_rdy is High.

If app_wdf_rdy is deasserted, the user logic needs to hold app_wdf_wren and app_wdf_end High along with the valid app_wdf_data value until app_wdf_rdy is reasserted. 

When using data masking, the app_wdf_mask signal can be used to mask out the bytes to write to external memory.

The maximum delay for a single write between the write data and the associated write command is two clock cycles. 

When issuing back-to-back write commands, there is no maximum delay between the write data and the associated back-to-back write command.

The app_wdf_end signal must be used to indicate the end of a memory write burst. 

When a 2:1 PHY to controller clock ratio is used with a BL8 command, the app_wdf_end signal must be asserted on the second write data word. 

The app_wdf_en signal can be held High during a series of several bursts with the app_wdf_end signal asserted at the end of each individual burst. 

For a 4:1 PHY to controller clock ratio, app_wdf_end is asserted on every data word. 

The app_wdf_end signal will not be accepted while app_wdf_rdy is Low, in which case the last word of a data burst and app_wdf_end should be held High until app_wdf_rdy asserts for one cycle.

When the memory burst type is set to BC4, the last four bits of the burst are masked. 

The DDR3 SDRAM provides the on-the-fly (OTF) mode and allows the user logic to change the memory burst type via the A12 address bit.

The user can end a write transaction earlier for four write bits by asserting the app_wdf_end signal.


  • The MIG controller presents a flat address space to the user interface and translates it to the addressing required by the SDRAM.
  • The burst order for a write with BL=8 will always start at column address 0 and count up sequentially to 7.
    While for a BL=4 (or Burst Chop of 4), the starting column address will either be 0 (A3 = 0) or 4 (A3 = 1).
    For more details on burst addressing, see the appropriate JEDEC specification.
Additional Information

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AR# 34677
Date 11/28/2014
Status Active
Type Solution Center
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-7
  • Kintex-7
  • Artix-7
  • Zynq-7000
  • Less
  • MIG
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