This part of the MIG Design Assistant will guide you to information on performing writes to the User Interface.
NOTE: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243)
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Driving Write on the User Interface
The write data is registered in the write FIFO when app_wdf_wren is asserted and app_wdf_rdy is High.
If app_wdf_rdy is deasserted, the user logic needs to hold app_wdf_wren and app_wdf_end High along with the valid app_wdf_data value until app_wdf_rdy is reasserted.
When using data masking, the app_wdf_mask signal can be used to mask out the bytes to write to external memory.
The maximum delay for a single write between the write data and the associated write command is two clock cycles.
When issuing back-to-back write commands, there is no maximum delay between the write data and the associated back-to-back write command.
The app_wdf_end signal must be used to indicate the end of a memory write burst.
When a 2:1 PHY to controller clock ratio is used with a BL8 command, the app_wdf_end signal must be asserted on the second write data word.
The app_wdf_en signal can be held High during a series of several bursts with the app_wdf_end signal asserted at the end of each individual burst.
For a 4:1 PHY to controller clock ratio, app_wdf_end is asserted on every data word.
The app_wdf_end signal will not be accepted while app_wdf_rdy is Low, in which case the last word of a data burst and app_wdf_end should be held High until app_wdf_rdy asserts for one cycle.
When the memory burst type is set to BC4, the last four bits of the burst are masked.
The DDR3 SDRAM provides the on-the-fly (OTF) mode and allows the user logic to change the memory burst type via the A12 address bit.
The user can end a write transaction earlier for four write bits by asserting the app_wdf_end signal.