My design was working fine in ISE Design Suite 11.4, but since I have upgraded to 11.5, the following DRC errors occur when I run BitGen:
"ERROR:PhysDesignRules:1422 - Dangling pins onblock:
RAM5_RAMD >:< LUT_OR_MEM5 >. With dual or single port RAM programming the DI1 and WA1-WA5 pins must be connected.
ERROR:PhysDesignRules:1385 - Dangling pins onblock:< Hard_Ethernet_MAC/
< LUT_OR_MEM6 >. For RAMMODE programming set with DPRAM32 or SPRAM32 or SRL16 the DI2 input pin must be connected."
Is this a known problem?
This problem is a regression in trimming in ISE Design Suite11.5 related to LUTRAM inputs. The problem is fixed for 12.1, and a patch is available for 11.5.
To Install:, unzip 34693_map_115_nt.zip in the XILINX installdirectory while maintaining directory structure.
To Install:, unzip 34693_map_115_nt64.zip in the XILINX installdirectory while maintaining directory structure.
NOTE: Not all occurrences of these errors are due to trimming bugs. This Answer Record is only a good match for your case if the error is occurring in ISE Design Suite 11.5 and appears to be due to invalid trimming of LUTRAM inputs.