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AR# 34699

Block Memory Generator v3.3 - Spartan-6 Block RAM Read First mode address space overlap ("collision") issue with simultaneous Read and Write may cause memory corruption


Block RAM collisions occur in the following Block Memory Generator configurations and conditions:

  • True Dual Port (TDP) or Simple Dual Port (SDP) configuration
  • Application performs a simultaneous Read and Write
  • Either port A or port B, or both ports are configured with Write Mode configured as Read First.


In the above conditions users need to make sure that the certain address bits of the Port-A and Port-B addresses do not match to avoid memory collisions. Violating this restriction may result in incorrect operation of BRAM.

  • When CLKA and CLKB are driven by different clocks (asynchronous clocks), and for RAMB8BWER (A12-A6, A4) or RAMB16BWER ( A13-A6, A4) match for Port-A and Port-B addresses.
  • Collisions will not occur when CLKA and CLKB are driven by same clock buffer and when skew between CLKA and CLKB is less than 100 ps.

For details, refer to the Asynchronous Clocking section under Conflict Avoidance in the Spartan-6 Memory Resources User Guide (UG383), which documents the issue as follows:

In READ_FIRST mode only, the dual-port block RAM has the additional restriction that addresses for port A and B cannot collide. This applies for both TDP and SDP modes.

A read/write on one port and a write operation from the other port at the same address is not allowed. This restriction on the operation of the block RAM should not be ignored.

RAMB16BWER when both ports are 18 bits wide or smaller: A13A6, including A4, cannot be the same.
RAMB16BWER when any one port is 36 bits wide: A13A7, including A5, cannot be the same.
RAMB8BWER in all configurations: A12A6 including A4 cannot be the same

Users generating S6 block memory design using block Memory Generator versions earlier thanv3.3 should migrate tov4.1 available with ISE Design Suite 12.1(duein May 2010). Workarounds based on v3.3 Block Memory Generator configuration:

1. When the user selects SDP Fixed Primitives 256x36
o Solution: Internally, core uses 512x36 primitives
o Impact: Memory utilization doubles
2. When the user selects SDP Fixed Primitives Other than 256x36 primitives
o Solution: No Change
o Impact: None
3. When the user selects SDP Minimum Area or Low Power algorithm
o Solution: Internally, core does not use 256x36 primitive
o Impact: Memory utilization might double based on user depth x width selection
4. When the user selects TDP RF/WF/NC modes
o Solution: No Change
o Impact: When write_mode= Read First, the user has to consider the collision issue as specified above
5. For generated cores with Mux Pipeline Stages enabled, it is recommended to recreate the core using CORE Generator Flow and re-select the Mux pipeline stages.

AR# 34699
Date Created 10/18/2010
Last Updated 06/27/2012
Status Active
Type Known Issues
  • Spartan-6 LX
  • Spartan-6 LXT
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • More
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
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  • Block Memory Generator