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AR# 34709

MIG Virtex-6 DDR2/DDR3 - Debugging Data Errors


Data errors can be see post calibration for many reasons. When a data error occurs, there are steps that should be followed to debug the cause of the error(s). This answer record focuses on the recommended steps to debug the root cause of data errors.

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


Isolating Data Errors

Isolate the Error:

Data errors in hardware can point to many different board level issues such as crosstalk or stuck bits. The first step in debugging a root cause for a data error, is to isolate the data error(s).

  • Are errors seen on data bits belonging to certain DQS groups?
  • Are errors seen on accesses to certain addresses, banks, or ranks of memory?
  • Do the errors only occur for certain data patterns or sequences?

Determine if the error is due to the write or read:

The root cause of a data error can come from either a write or a read. The next step is then to determine whether the memory device received incorrect data during a write or if the data became corrupted on the read.

The Virtex-6 FPGA Memory Interface Solutions User Guide includes a section on Data Errors in the Debug Guide. Please see the DDR2/DDR3 SDRAM Memory Interface Solution > Debugging Virtex-6 FPGA DDR2/DDR3 SDRAM Designs > Isolating Data Errors section for more details on isolating the error and determining whether the error occurs during a write or read.

For additional information on isolating the write versus the read causing problems, please see (Xilinx Answer 35209).

Test board with different data patterns using the Traffic Generator:

MIG includes a Traffic Generator with the provided Example Design that can be used to help isolate data errors. The traffic generator can be configured to send many different traffic patterns that test for different board issues. For example, sending a "hammer" pattern with switching ones and zeros will stress SSO while sending "PRBS" tests more real world patterns. For more information on the traffic generator and how to configure it to test different data patters, please see:

Small Data Valid Window
Data errors can also be seen when a small data valid window was found during calibration. This is because during normal operation, the data patterns will be "tougher" causing a smaller eye due to more logic switching. This results in more switching related noise.

Adherence to the Virtex-6 FPGA DDR2/DDR3 MIG board layout guidelines ensure a proper data valid is found during calibration. However, not following the guidelines can result in either calibration failures or a small data valid window. It is important to go through a general hardware debug flow and verify the MIG guidelines have been followed.

For general board level debug, please see:

To calculate the read data valid window post calibration, please see:

For information on the Virtex-6 DDR2/DDR3 MIG Board Layout Guidelines, please see:

For information on debugging calibration failures, please see:

Linked Answer Records

Associated Answer Records

AR# 34709
Date Created 06/16/2010
Last Updated 12/15/2012
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
  • MIG