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AR# 34712 Design Advisory for Spartan-6 FPGA Block RAM - 9K Simple Dual Port (SDP) Block RAM Initialization Incorrect

Description

Initialization of the 9Kb block RAM in SDP mode is not correctly performed in ISE Design Suite 11.5. This issue has been fixed in ISE software12.1 and later.

Solution

Issue Description

When using the 9K block RAM in SDP mode with ISE 11.5 and earlier software, the block RAM might not have the proper memory array initialization values.When attempting to initialize to anything but the default of all zeros, the actual initialized value in the block RAM might not be as expected.

Affected Components

RAMB8BWER in SDP mode with INITs or INIT_FILE set to anything but the default all zeros.This can also occur via synthesis inference, use of UNIMacro block RAM components, use of memory generator with a COE file, and the use of some cores that contain the affected block RAM.

Software Affected

  • InISE Design Suite11.5 and earlier- Simulation andFPGA Editorshow proper INIT strings, however, the data placed into the block RAM can appear corrupt. Hardware testing is the only valid way to determine if initializationhas occurred correctly.
  • In ISE Design Suite12.1 and later - This issueisresolved in the 12.1 version ofthe ISE software.9K block RAM initializes correctly, and is reflected in simulation and FPGA Editor views.

Work-around

There is no work-around in the ISE 11.5 and earlier software.Until a fix is available in ISE 12.1, avoid initializing the RAMB8BWER to anything except for all zeros.

Note: There are other issues that might affect your design while using the Spartan-6 Block RAM in this configuration.Please see (Xilinx Answer 32651) in the Block RAM section for all known issues, including other initialization issues and a port width restriction for 9K block RAM in SDP mode.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34856 Design Advisory Master Answer Record for Spartan-6 FPGA N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
46792 Spartan-6 FPGA Design Assistant - Troubleshoot common block RAM/FIFO problems N/A N/A
35395 LogiCORE IP Motion Adaptive Noise Reduction v1.0 - Spartan-6 core should only be gnerated in 12.1 an later due to potential block RAM memory related problems N/A N/A
35382 LogiCORE IP Video Scaler v2.0 - Virtex-6 and Spartan-6 core should not be used in production due to potential block RAM memory related problems N/A N/A
34856 Design Advisory Master Answer Record for Spartan-6 FPGA N/A N/A
32651 Spartan-6 - ISE Software 11 Update Known Issues related to Spartan-6 FPGA N/A N/A
39999 Design Advisory for Spartan-6 FPGA - 9K Block RAM Initialization Support N/A N/A

Actions

AR# 34712
Date Created 03/22/2010
Last Updated 11/15/2012
Status Active
Type Design Advisory
Devices
  • Spartan-6 LX
  • Spartan-6 LXT
Tools
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • More
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • Less
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