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AR# 34713 Spartan-6 FPGA Block RAM - INIT_FILE Attribute on 9K Block RAM Does Not Initialize Correctly

Description

Initialization of the 9K block RAM (RAMB8BWER primitive) using the INIT_FILE attribute does not work correctly unless set to the default value.

Solution

Issue Description

When using the RAMB8BWER in any mode, the INIT_FILE attribute does not correctly initialize the block RAM. When using the INIT_FILE attribute to set values to anything but the default zero, initialization is shown for simulation of both pre-synthesis and timing simulation, but the hardware does not reflect those same values.

Affected Components

RAMB8BWER in any mode where INIT_FILE is set to anything but the default zero values.

Software Behavior

  • ISE Design Suite 11.5 and earlier - Simulation appears to have proper memory contents, but those contents are not reflected in the actual initialized values on the device.
  • ISE Design Suite 12.1 and later - A Design Rules Check (DRC) has been added to the UNISIM and SIMPRIM models so that an error is issued any time the INIT_FILE is a non-default value. The DRC is removed when INIT_FILE initialization is properly supported.

Work-around

Do not use the INIT_FILE attribute. You must use the INIT attributes instead and cannot perform post-synthesis update of memory contents for the RAMB8 blocks. More information can be found in the Spartan-6 Libraries Guide under the RAMB8BWER primitive:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/spartan6_hdl.pdf

NOTE: When using the INIT attributes, please be aware of the 9K block RAM initialization issue in (Xilinx Answer 34712).

Actions

AR# 34713
Date Created 03/19/2010
Last Updated 05/26/2010
Status Active
Type
Devices
  • Spartan-6 LX
  • Spartan-6 LXT
Tools
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • More
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • Less
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