AR# 34718 MIG Virtex-6 DDR2/DDR3 - PHY Architecture
Description
The Virtex-6 MIG DDR2/DDR3 design is divided into three main components - the user interface, controller and PHY as shown here:
The PHY provides a physical interface to an external DDR2 or DDR3 SDRAM. The PHY generates the signal timing and sequencing required to interface to the memory device. It contains the clock-, address-, and control-generation logic, write and read datapaths, and state logic for initializing the SDRAM memory after power-up. In addition, the PHY contains calibration logic to perform timing training of the read and write data paths to account for system static and dynamic delays.
The Virtex-6 Memory Interface Solutions User Guide includes a detailed section on the PHY logic. Please review this material within the DDR2/DDR3 SDRAM Memory Interface Solution > Core Architecture > PHY section.
NOTE: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
Solution
PHY Signal and Parameter Description- (Xilinx Answer 34923)
PHY Initialization and Calibration Steps- (Xilinx Answer 34740)
PHY Architecture Design - (Xilinx Answer 35189)
DFI Interface - (Xilinx Answer 35164)
Stand Alone PHY Support- (Xilinx Answer 35168)
Linked Answer Records
Associated Answer Records
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 35168 | MIG Virtex-6 DDR2/DDR3 - Stand alone PHY support | N/A | N/A |
| 34923 | MIG Virtex-6 DDR2/DDR3 Solution Center Design Assistant - Design Signal and Parameter Descriptions | N/A | N/A |
| 34282 | MIG Design Assistant - Virtex-6 Core Functionality | N/A | N/A |
| 34740 | MIG Virtex-6 DDR2/DDR3 - PHY Initialization and Calibration | N/A | N/A |