The Virtex-6 MIG DDR2/DDR3 design is divided into three main components - the user interface, controller and PHY as shown here:
The PHY provides a physical interface to an external DDR2 or DDR3 SDRAM. The PHY generates the signal timing and sequencing required to interface to the memory device. It contains the clock-, address-, and control-generation logic, write and read datapaths, and state logic for initializing the SDRAM memory after power-up. In addition, the PHY contains calibration logic to perform timing training of the read and write data paths to account for system static and dynamic delays.
The Virtex-6 Memory Interface Solutions User Guide includes a detailed section on the PHY logic. Please review this material within the DDR2/DDR3 SDRAM Memory Interface Solution > Core Architecture > PHY section.
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