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AR# 34744

MIG 7 Series and Virtex-6 DDR2/DDR3 - PHY DDR2/DDR3 Initialization

Description

The MIG 7 Series and Virtex-6 DDR2/DDR3 designs' first stage of initialization and calibration is to complete the required DDR2/DDR3 SDRAM initialization sequence as defined by the Jedec Standard. MIG is compliant to the required initialization for DDR2 and DDR3 as defined in:

  • DDR2 SDRAM Jedec Standard - Sections 2.3 and 2.4
  • DDR3 SDRAM Jedec Standard - Sections 3.3 and 3.4

NOTE: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

Mode Registers

Each DDR2 or DDR3 SDRAM has a series of mode registers, accessed via mode register set (MRS) commands. These mode registers determine various SDRAM behaviors, such as burst length, read and write CAS latency, and additive latency. The particular bit values programmed into these registers are configurable through the MIG GUI on the Memory Options screen. These GUI settings properly set top-level HDL parameters in the MIG output. These parameters should not be modified manually. Please rerun the MIG tool to change a mode register setting.

Initialization During Simulation

MIG generates a simulation testbench in the output 'example_design/sim' and 'user_design/sim' directories. This simulation testbench sets a simulation only parameter to skip the long set-up wait times defined by the DDR2/DDR3 standards.

For Virtex-6 devices, the simulationparameter settingis SIM_INIT_OPTION = SKIP_PU_DLY. This should only be set to SKIP_PU_DLY in a simulation environment. In the top level rtl, please ensure SIM_INIT_OPTION = NONE. This ensures the PHY executes the full required DDR2/DDR3 SDRAM initialization process. MIG properly sets this parameter to NONE in the provided top level rtl for both the Example Design and the User Design.

For 7 series FPGAs, the simulation parameter setting is SIM_BYPASS_INIT_CAL = FAST. This should only be set to FAST in a simulation environment. In the top level rtl, please ensure SIM_BYPASS_INIT_CAL = OFF. This will ensure the PHY executes the full required DDR2/DDR3 SDRAM initialization process. MIG properly sets this parameter to NONE in the provided top level rtl for both the Example Design and the User Design.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
51954 MIG 7 Series DDR2/DDR3 - PHY Initialization and Calibration N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34740 MIG Virtex-6 DDR2/DDR3 - PHY Initialization and Calibration N/A N/A
AR# 34744
Date Created 05/24/2010
Last Updated 09/26/2012
Status Active
Type Solution Center
Devices
  • Virtex-6
  • Virtex-7
IP
  • MIG Virtex-6 and Spartan-6
  • MIG 7 Series