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AR# 34756

Xilinx ISE Implementation Tools Solution Center - Design Assistant


Please refer to the following to learn more about designing with the Xilinx ISE Implementation Tools or to find help on debugging an issue you are currently encountering.

NOTE: This answer record is part of the Xilinx ISE Implementation Tools Solution Center (Xilinx Answer 34752). The Xilinx ISE Implementation Tool Solution Center is available to address questions related to Xilinx ISE Implementation Tools.


The Xilinx Implementation Tools have four major functional areas:

For the MAP section of the Xilinx ISE Implementation Tools Design Assistant, see (Xilinx Answer 35438).

In this context MAP refers to the front end and back end of the MAP application which also performs packing and placement. The front end involves the processing of the input logical netlist which can involve retargeting logical instances to newer symbols, the trimming of unused logic and optimization of constant logic, expanding symbols into one or more other symbols and running Logical DRC (LIT messages) to check for issues with the logical netlist. At the back end Physical DRC (PhysDesignRules messages) checks the physical design implementation and finally the printing of the map report (.mrp file) which includes device utilization and other information. MAP also covers the resynthesis options Global Opt which optimized the logical netlist on the front end and Logic Opt that optimizes the physical implementation at the back end.

For the PACK section of the Xilinx ISE Implementation Tool Design Assistant, see (Xilinx Answer 35439).

Packing is the conversion of symbols from the logical netlist into physical elements, either BELs or Components. BELs (Basic Element of Logic) are handled by the placer before a component is assembled, i.e. a LUT or FF BELs will be manipulated by the placer before being assembled into a Slice component. The PACK process begins with Directed packing which assembles components and macros based on packing constraints and also assembles system macros based on connectivity, i.e. carry chain system macros are built at this time to align the carry structure. Packing continues with Delay-Based LUT Packing phase which constructs physical LUTS from logical LUTs, LUTRAM and SRLs. LUT-FF pairs are also created as single entities. At this point timing models are built for the physical implementation and the placement phases are run. After placement PACK constructs components from the placed BELs.

For the PLACE section of the Xilinx ISE Implementation Tool Design Assistant, see (Xilinx Answer 35440).

Placement refers to arrangement of BELs and Components into physical sites on the devices such that routing is feasible and can meet timing constraints. The placement process begins with some feasibility checks and then I/O and clock components are placed together because of their interdependence. A second phase of clock placement is run to constrain the clock loads so that all clocking restrictions are met before general placement begins. A clock distribution report is printed at this point so that the automatic floorplanning of the design can be observed. Various optimizations are run along the way. Phase X.8 (Global Placement) is the general placement phase and it is at this point that the placer attempts to entirely fit the design. If the design is difficult to fit, multiple passes and/or slow run time may be observed. A final placement verification is run before the design is passed back to the packer for final component creation.

For the ROUTE section of the Xilinx ISE Implementation Tool Design Assistant, see (Xilinx Answer 35441).

Routing refers to the creation of pin to pin connections between components that completes the physical implementation of the design. The router needs to find routing resources that complete all connections while meeting all timing constraints. This can be made difficult if the design is either congested, has aggressive timing constraints or if the router has to work with a poor placement. Long run time can be attributed to one or a combination of these factors.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34752 Xilinx ISE Implementation Tools Solution Center N/A N/A

Associated Answer Records

AR# 34756
Date 04/04/2017
Status Active
Type Solution Center
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