UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 34760

Simulation - How do I write an efficient testbench?

Description

Does Xilinx provide any guidelines for writing HDL testbenches?

Solution


Xilinx provides an Application Note forlogic designers who are new to HDL verification flows andwho do not have extensive testbench-writing experience. Testbenches are the primary means of verifying HDL designs.
The Writing Efficient Testbenches Application Note (XAPP199)providesguidelines for laying out and constructing efficient testbenches. It also provides an algorithm todevelop a self-checking testbench for any design:
http://www.xilinx.com/support/documentation/application_notes/xapp199.pdf
You can also find testbench templates (both in Verilog and VHDL) in the Language Templates in Project Navigator (Edit -> Language Templates).
AR# 34760
Date Created 07/20/2010
Last Updated 02/14/2013
Status Active
Type General Article
Tools
  • ISE - 10.1
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • More
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • Less