LogiCORE IP Tri-Mode Ethernet MAC v4.4 and earlier - Virtex-6 FPGA block RAM parameterization might result in memory collisions during simulation and erroneous operation

Description

When I target Virtex-6 FPGA in the LogiCORE Tri-Mode Ethernet MAC version 4.4 and earlier, block RAM instances do not comply with all asynchronous clocking conflict avoidance requirements as described in the Virtex-6 FPGA Memory Resources User Guide (UG363):
http://www.xilinx.com/support/documentation/user_guides/ug363.pdf

Specifically, RAMB16_S9_S9 instances within the LocalLink FIFO level of hierarchy are configured for READ_FIRST TDP mode, but do not respect the requirement that read and write addresses cannot be within the same page of memory. When using ISE tools 11.4, this might result in memory collisions reported during simulation. Additionally, using ISE tools 11.3 or 11.4 might result in marginal or erroneous hardware operation of the block RAM.

Solution

Files named "rx_client_fifo.v[hd]" and "tx_client_fifo.v[hd]" exist in the example_design/fifo subdirectory. In each, there are instances of the primitive RAMB16_S9_S9 which contains attributes called WRITE_MODE_A and WRITE_MODE_B. To workaround this issue, change both the WRITE_MODE_A and WRITE_MODE_B values from "READ_FIRST" to "WRITE_FIRST".

This issue was fixed in version 4.3 rev2 available the ISE design tools 11.5 release of the core, but still exists in the version 4.4 core released in 12.1.  This issue is scheduled to be fixed in the next release of the core.