Spartan-6 PLL - Incorrect Compensation Mode Set

Description

The ISE Design Suite 11.5 software incorrectly sets the compensation mode for the PLL.  This will have timing implications when performing timing analysis.

Solution

Issue Description:

When the PLL compensation is set to ?SYSTEM_SYNCHRONOUS?, the PLL input delays are not being set to ensure zero hold times. The problem is caused by the ISE Design Suite 11.5 software not correctly setting the PLL settings. The timing information delivered in the timing analysis tools is based on SYSTEM_SYNCHRONOUS being set, and will therefore be incorrect with respect to what is implemented in hardware.

Software Behavior:

This issue will be fixed in ISE Design Suite 12.1. The issue is present in ISE Design Suite 11.5 and earlier. 

Workaround:

All compensation settings besides SYSTEM_SYNCHRONOUS are correct for the PLL.  It is recommended to use SOURCE_SYNCHRONOUS compensation mode if possible in the design to ensure matching of the software timing tools and hardware behavior. 

For more information on the PLL and compensation settings, please refer to the Spartan-6 FPGA Clocking Resource User Guide (UG382).