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AR# 34777 Design Assistant for PCI Express - Device not recognized by system

Description

This Answer Record gives possible reasons why a device is not being recognized by the system. In some cases, the system boot fines, but the driver cannot recognize or interface with the device.

NOTE: This Answer Record is part of the Xilinx Solution Center for PCI Express (Xilinx Answer 34536) Xilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIe to guide you to the right information.

Solution

  1. Determine if the device is not recognized at all or if it is recognized, but did not get configured (meaning the BARs are not set). To do this, use a tool such as PCITree (Windows-32), HWDirect (Windows-64), or lspci (Linux).For more information on these tools and how to use them, see (Xilinx Answer 34806)
  2. A possible cause is that the FPGA was not configured in time to be enumerated and configured by the system software (BIOS). A quick test for this is after the system boots from power on, issue a warm restart to see if the endpoint is recognized. During a warm restart, the system power remains on to the board so that the FPGA does not have to reconfigure.For more information on FGPA configuration in regards to PCI Express, see (Xilinx Answer 34800)
  3. If a warm restart does not help, the next step is to determine the status of trn_lnk_up and trn_reset_n. These are outputs of the core to the user application and are key indicators to the status of the endpoint.For more information on using these signals to debug the problem, see (Xilinx Answer 34873) .
  4. If you used JTAG to configure the device after the system was powered, see (Xilinx Answer 34871)
  5. See (Xilinx Answer 37406) regarding a method on Linux to copy and reinstate the endpoint's configuration space if you want to re-configure the FPGA after PCIe enumeration has occurred.

Revision History
08/13/2010 - Initial Release
10/08/2010 - Added reference to 37406.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
37406 Design Assistant for PCI Express - How to enumerate the endpoint when FPGA is configured after enumeration. N/A N/A
34873 Design Assistant for PCI Express - Debugging System Recognition and Link Training Issues Using trn_lnk_up_n and trn_reset_n N/A N/A
34871 Design Assistant for PCI Express - Using JTAG to Configure the Device N/A N/A
34800 Design Assistant for PCI Express - Problems Associated with FPGA Configuration N/A N/A
34538 Xilinx Solution Center for PCI Express - Design Assistant N/A N/A
34085 Design Assistant for PCI Express - Hardware Debug N/A N/A
34806 Design Assistant for PCI Express - Software that Displays PCI Express Devices In System N/A N/A

Actions

AR# 34777
Date Created 08/03/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Spartan-6 LXT
  • Virtex-5 FXT
  • Virtex-5 LXT
  • More
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-6 CXT
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6 HXT
  • Less
IP
  • Endpoint Block Plus Wrapper for PCI Express
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
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