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AR# 34779

MIG 7 Series and Virtex-6 DDR2/DDR3 - User Interface - Addressing

Description

This part of the MIG Design Assistant will guide you to information on addressing at the User Interface.

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243) The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

General Addressing Guidelines

  • The MIG controller presents a flat address space to the user interface and translates it to the addressing required by the SDRAM.
  • The MIG controller supports sequential and interleaved reads; this option is set in the GUI at generation time.

For a visual view of the address mapping, please see the Memory Address Mapping in UI Module figure in UG406 and UG586.

Burst Wrapping

Reads

  • The burst order for a sequential read with BL=8 will start at the column address specified and increment sequentially but wrap around after address 3 and 7. The burst is divided into the top 4 and bottom 4 address locations. For example, for a Column Address of 011, the data returned will be follow the sequence: 3,0,1,2,7,4,5,6. While for a Column address of 101, the data returned will follow the sequence 5,6,7,4,1,2,3,0. This adheres to the JEDEC Standard.
  • For an interleaved read, the order of the data coming back will follow a similar pattern but will also be interleaved. For example, for Column Address of 011 the data returned will follow the sequence: 3, 2, 1, 0, 7, 6, 5, 4. For more information see the DDR2/DDR3 JEDEC specification.
  • For more information on sequential and interleaved burst order see DDR2 SDRAM Standard JESD79-2C (Table 9) or DDR3 SDRAM Standard JESD79-3 (Table 3).
  • For a burst chop of 4 (DDR3 only), there will be four cycles of valid data followed by four cycles of invalid data. For more details on burst addressing, see the DDR3 JEDEC Standard..

Writes

  • The burst order for a write with BL=8 will always start at column address 0 and count up sequentially to 7. While for a BL=4 (or Burst Chop of 4), the starting column address will either be 0 (A3 = 0) or 4 (A3 = 1). For more details on burst addressing, see the appropriate JEDEC spec.
  • When the memory burst type is set to BC4, the last four bits of the burst are automatically ignored by the SDRAM.

For timing diagrams and more information, see the DDR2 and DDR3 Interface Solution > Interfacing to the Core section of UG586 and UG406.

For information on sending reads and writes, please see (Xilinx Answer 33698)

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
33698 MIG 7 Series and Virtex-6 FPGA DDR2/DDR3 - How do I drive the user interface? N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
33698 MIG 7 Series and Virtex-6 FPGA DDR2/DDR3 - How do I drive the user interface? N/A N/A
AR# 34779
Date Created 05/24/2010
Last Updated 10/04/2012
Status Active
Type Solution Center
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-7
  • Kintex-7
  • Artix-7
  • Zynq-7000
  • Less
IP
  • MIG