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AR# 34780

MIG 7 Series and Virtex-6 DDR2/DDR3 - User Interface - Masking Data

Description

This part of the MIG design assistant guidesyou to information on Masking Data with the User Interface.

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

Data Mask is an option in the MIG GUI and can be deselected to save pins.

Data masking occurs on a per byte basis (cannot mask individual bits).The user interface uses the input app_wdf_mask[APP_MASK_WIDTH - 1:0] to determine the bytes masked during a write.This corresponds to the signal ddr_dm[(DQ_WIDTH/8) - 1:0] at the top level, which goes out to the memory.

For timing diagrams and more information, see UG406 and UG586 under DDR2 and DDR3 Interface Solution > Interfacing to the Core.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
33698 MIG 7 Series and Virtex-6 FPGA DDR2/DDR3 - How do I drive the user interface? N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
33698 MIG 7 Series and Virtex-6 FPGA DDR2/DDR3 - How do I drive the user interface? N/A N/A
AR# 34780
Date Created 05/24/2010
Last Updated 10/04/2012
Status Active
Type Solution Center
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-7
  • Kintex-7
  • Artix-7
  • Zynq-7000
  • Less
IP
  • MIG