We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 34781

LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII v10.3 - Virtex-6 FPGA block RAM parameterization might result in memory collisions during simulation and erroneous operation


When I target a Virtex-6 FPGAin the LogiCOREEthernet 1000BASE-X PCS/PMA or SGMII version 10.3 and earlier, block RAM instances do not comply with all asynchronous clocking conflict avoidance requirements as described in the Virtex-6 FPGA Memory Resources User Guide (UG363):

Thisproblem only existswhen the core is generated with theoptional fabricelastic buffer for SGMII mode for Virtex-6 devicesandcould result in memory collisions and erroneous behavior.


This issue has been corrected in theLogiCOREEthernet 1000BASE-X PCS/PMA or SGMII version 10.3 rev1 and later,available starting in ISE Design Suite 11.5.

Linked Answer Records

Master Answer Records

Associated Answer Records

AR# 34781
Date Created 03/16/2010
Last Updated 12/15/2012
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • More
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • Less
  • Ethernet 1000BASE-X PCS/PMA or SGMII