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AR# 34781

LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII v10.3 - Virtex-6 FPGA block RAM parameterization might result in memory collisions during simulation and erroneous operation

Description

When I target a Virtex-6 FPGAin the LogiCOREEthernet 1000BASE-X PCS/PMA or SGMII version 10.3 and earlier, block RAM instances do not comply with all asynchronous clocking conflict avoidance requirements as described in the Virtex-6 FPGA Memory Resources User Guide (UG363):
http://www.xilinx.com/support/documentation/user_guides/ug363.pdf.

Thisproblem only existswhen the core is generated with theoptional fabricelastic buffer for SGMII mode for Virtex-6 devicesandcould result in memory collisions and erroneous behavior.

Solution

This issue has been corrected in theLogiCOREEthernet 1000BASE-X PCS/PMA or SGMII version 10.3 rev1 and later,available starting in ISE Design Suite 11.5.

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AR# 34781
Date Created 03/16/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT
Tools
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • More
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • Less
IP
  • Ethernet 1000BASE-X PCS/PMA or SGMII