LogiCORE IP 10-Gigabit Ethernet MAC v9.3 - Virtex-6 FPGA block RAM parameterization might result in memory collisions during simulation and erroneous operation
Description
When I target Virtex-6 FPGA in the 10-Gigabit Ethernet MAC version 9.3 and earlier, block RAM instances do not comply with all asynchronous clocking conflict avoidance requirements as described in the Virtex-6 FPGA Memory Resources User Guide (UG363):
http://www.xilinx.com/support/documentation/user_guides/ug363.pdf.
This problem only exists when the example design local link FIFO is used and could result in memory collisions and erroneous behavior.
Solution
This issue has been corrected in the 10-Gigabit Ethernet MAC version 9.3 rev1 and later available starting in ISE design tools 11.5.
Applies To
Devices
- Virtex-6 CXT
- Virtex-6 HXT
- Virtex-6 LXT
- Virtex-6 SXT
Design Tools
- ISE Design Suite - 11.1
- ISE Design Suite - 11.2
- ISE Design Suite - 11.3
- ISE Design Suite - 11.4
- ISE Design Suite - 11.5
IP
- 10 Gigabit Ethernet Media Access Controller