^
Advanced Search

AR# 34783 LogiCORE IP 10-Gigabit Ethernet MAC v9.3 - Virtex-6 FPGA block RAM parameterization might result in memory collisions during simulation and erroneous operation

Description

When I target Virtex-6 FPGA in the10-Gigabit Ethernet MAC version 9.3 and earlier, block RAM instances do not comply with all asynchronous clocking conflict avoidance requirements as described in the Virtex-6 FPGA Memory Resources User Guide (UG363):
http://www.xilinx.com/support/documentation/user_guides/ug363.pdf.

Thisproblem only existswhen theexample design local linkFIFO is used andcould result in memory collisions and erroneous behavior.

Solution

This issue has been corrected in the10-Gigabit Ethernet MAC version 9.3 rev1 and lateravailable starting in ISE design tools 11.5.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
33304 LogiCORE IP 10-Gigabit Ethernet MAC v9.3 and v9.3 rev1 - Release Notes and Known Issues for ISE 11.3 and ISE 11.5 N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
33304 LogiCORE IP 10-Gigabit Ethernet MAC v9.3 and v9.3 rev1 - Release Notes and Known Issues for ISE 11.3 and ISE 11.5 N/A N/A

Actions

AR# 34783
Date Created 03/16/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT
Tools
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • More
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • Less
IP
  • 10 Gigabit Ethernet Media Access Controller
Feed Back