We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

AR# 34803

Spartan-6 Block RAM - 9Kb Block RAM SRVAL/INIT Values Incorrect for Parity Bits


SRVAL and INIT values may not be properly set for the 9K Block RAM parity bits.


The parity bits SRVAL and INIT values are not being set properly for Spartan-6 FPGA 9k Block RAM when the DATA_WIDTH = 9.

Affected components:
RAMB8BWER when the DATA_WIDTH is set to 9

Software Behavior:

  • Behavior in ISE Design Suite 11.5 and earlier: The parity bit in 9-bit mode may have incorrect SRVAL and/or INIT programmed.
  • Behavior in ISE Design Suite 12.1 and later: This will be fixed in this version of software. SRVAL and INIT values will be properly set.


There is no workaround at this time.

AR# 34803
Date 05/26/2010
Status Active
Type General Article
  • Spartan-6 LX
  • Spartan-6 LXT
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • More
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • Less