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AR# 34811

XST - ERROR:HDLCompiler:661 - Non-net port clk_i cannot be of mode input

Description

I have a design that synthesized successfully when I target devices older than Spartan-6/Virtex-6 FPGA. However for Spartan-6/Virtex-6 FPGA, I encounter the following error. Why?

ERROR:HDLCompiler:661 - "<verilog file>" Line #: Non-net port clk_i cannot be of mode input

Solution

XST is using a new parser starting with Virtex-6 and Spartan-6 FPGA which has enhanced language coverage and follows stricter LRM guidelines.

The error appears to occur when using the "`default_nettype none" to turn off automatic inference of wires in the design.

XST for Spartan-6 / Virtex-6 FPGA correctly issues an error for designs that declare port signals but do not implicitly declare wires for them. For example, the following code for a blackbox will issue the above error:

`default_nettype none // Do not to infer wiring.

modulemy_module

(
input clk ,//
inputreset ,//
inputdata_in ,//
outputdata_out //
);

This is in adherence to section 19.2 of the Verilog 2001 LRM.

For more help about this topic, please contact Technical Support using the Support contact information.

AR# 34811
Date Created 05/04/2010
Last Updated 12/15/2012
Status Active
Type General Article
Tools
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
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