Why does width expansion of FIFO require extra gating of FIFO36 signals?
As per UG363 page number 61 Figure 2-12, the Virtex-6 FPGA FIFO36 can be connected to add width to the design.
CLB logic is used to implement the AND/OR gates.
All of the FIFO FULL signals must be ORed together to created the
output FULL signal and all of the FIFO EMPTY signals must be ORed together
to create the output EMPTY signal.
The maximum frequency is limited by the logic gate feedback path.
The extra gating on WR acts as extra protection to avoid data corruption as the FIFO36 primitive guarantees no corruption on data even if you forget to pull down WR.
The extra gating on RD acts as an extra protection against outputting repetitive data.
It is not advised to write when the FIFO is FULL as this can corrupt the last written data.
This can be handled with
WERR, however, you will come to know only after a clock, by which point the next write
could have been issued which would lead to data corruption.
This also applies to the read side.
primitives may be placed far apart where one FIFO asserts/de-asserts
FULL/EMPTY earlier/later than other primitive.
Though the clocks are from same source, at the physical level 0 skew/phase difference is not guaranteed.
In this case the signals MUST be ORed to avoid data corruption.