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AR# 34845

FPGA - How do I place the GPIOs in tri-state until configuration is finished?


How do I hold the user I/Os in tri-state until configuration is finished?


During configuration

A hot-swap pin named HSWAPEN controls the user I/O's state during the configuration process (the name of this control pin varies by device families: it is PUDC_B for Extended Spartan-3A, HSWAP for Spartan-3E, HSWAP_EN for Spartan-3, Virtex-II and Virtex-II Pro FPGA, and HSWAPEN for Virtex-4 and Virtex-5 FPGA). When this pin is High, the internal pull-up resistors on each user I/O are disabled and theI/O is in high-Z state during configuration.

HSWAPEN is active on the rising edge of INIT_B. This means that forsituations where PROG_B held low during power up theI/O aretristated until PROG is released and INIT subsequently is released High.

There is an exception for the Spartan-3 family. HSWAP pull-ups are enabled on the falling edge of PROG_B or when the POR threshold is crossed rather than on the rising edge of INIT.

Pre-Configuration Power-Up

Independent of the hot-swap pin, on power-on, user I/Os of most FPGAsare placed in tri-state until configuration starts. VCCINT VCCAUX VCCO is the "golden sequence" that will always guarantee tri-stated I/Os. There is an exception for Spartan-3 Generation devices which is documented in (Xilinx Answer 32653).

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
39554 Spartan-6 - PUDC enabled Pullup timing N/A N/A
AR# 34845
Date Created 04/29/2010
Last Updated 01/23/2013
Status Active
Type General Article
  • Spartan-3
  • Spartan-3A
  • Spartan-3A DSP
  • More
  • Spartan-3AN
  • Spartan-3E
  • Virtex-4 FX
  • Virtex-4 LX
  • Virtex-4 SX
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-II
  • Virtex-II Pro
  • Virtex-II Pro X
  • Spartan-6 LXT
  • Spartan-6 LX
  • Less