We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 3486

SYNPLIFY: How are asynchronous set/reset flip-flops (DFFRS) handled?


Keywords: synplify, dffrs

Urgency: Standard

General Description: How does Synplify handle asynchronous set/reset
flip-flops for Xilinx architectures?


The XC3000/a, xc4000/e/ex/xl/xv/xla, and xc5200 architectures do not
have an asynchronous set/reset flip-flop. So, it is unadvisable
to descibe a register in the HDL code which the targeting
architecture can not support. Xilinx does not recommend using
these types of flip-flops.

The xc2000, xc7000, xc9500, and Virtex have primitives available
for these type of flip-flops. The primitive FDCP maps to the

Synplify will synthesize the generic DFFRS component because there
is no corresponding primitive to infer. If this is the case, then
the HDL code needs to be modified to accomodate the targeting

The XC4000/E/EX/XL/XLA family registers have an asynchronous set or
reset, but not both at the same time on the same register.

However, Synplicity does supply XC4000 XNF netlists for a DFFRS
constructed out of latches (LDCP_1). The latches themselves are
constructed using cross-coupled gates. Make sure you either source
the directory with '-sd' option in Ngdbuild, or copy the appropriate
XNF file to your project directory so the Xilinx Alliance software is
directed to the files. These XNF netlists are located in the
C:\synplcty\lib\xilinx directory on the PC, and $SYNPLICITY/lib/xilinx
on the WS.
AR# 3486
Date Created 08/31/2007
Last Updated 09/28/2008
Status Archive
Type General Article