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AR# 34871 Design Assistant for PCI Express - Using JTAG to Configure the Device

Description

If you used JTAG to configure the device after the system was powered, you must issue a warm restart.

NOTE: This Answer Record is part of the Xilinx Solution Center for PCI Express (Xilinx Answer 34536). The Xilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIe to guide you to the right information.

Solution

Using JTAG after the system is booted is common during development. However, when you do this the endpoint might link train properly, but it is not enumerated or configured by the system, so it is not recognized at this point. Issue a warm restart and the endpointis recognized; see (Xilinx Answer 34806) for tools that show if the device has been recognized by the system).

See (Xilinx Answer 37406) for a possible workaround to this problem if using Linux.

Revision History
10/08/2010 - Added reference to 37406.
08/13/2010 - Initial Release

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
37406 Design Assistant for PCI Express - How to enumerate the endpoint when FPGA is configured after enumeration. N/A N/A
35000 Design Assistant for PCI Express - What happens if the power if the FPGA is re-configured, power is removed, or card removed during normal operation of the link N/A N/A
34806 Design Assistant for PCI Express - Software that Displays PCI Express Devices In System N/A N/A
34777 Design Assistant for PCI Express - Device not recognized by system N/A N/A
34538 Xilinx Solution Center for PCI Express - Design Assistant N/A N/A

Actions

AR# 34871
Date Created 08/03/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Spartan-6 LXT
  • Virtex-5 FXT
  • Virtex-5 LXT
  • More
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • Endpoint Block Plus Wrapper for PCI Express
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
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