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AR# 34873 Design Assistant for PCI Express - Debugging System Recognition and Link Training Issues Using trn_lnk_up_n and trn_reset_n

Description


This Answer Record discusses how to use trn_reset_n and trn_lnk_up_n to debug device recognition and link trainingproblems.
NOTE: This Answer Record is part of the Xilinx Solution Center for PCI Express (Xilinx Answer 34536) The Xilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIe to guide you to the right information.

Solution


The signal trn_reset_n indicates the reset sequence is complete and assertion of trn_lnk_up_n indicates the link is trained.
The signal trn_reset_n must deassert(go tologic 1)before the link can train; see (Xilinx Answer 34894) for reasons why trn_reset_n might not deassert.
If trn_reset_n deasserts properly, but trn_lnk_up_n does not assert, see (Xilinx Answer 36137) />
Revision History
08/13/2010 - Initial Release

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
36137 Design Assistant for PCI Express - trn_reset_n (user_reset_out for AXI) is deasserting, but trn_lnk_up_n (user_lnk_up_n for AXI) is not asserting N/A N/A
34894 Design Assistant for PCI Express - Using trn_reset_n to debug link training issues N/A N/A
34777 Design Assistant for PCI Express - Device not recognized by system N/A N/A
34538 Xilinx Solution Center for PCI Express - Design Assistant N/A N/A

Actions

AR# 34873
Date Created 08/03/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Spartan-6 LXT
  • Virtex-5 FXT
  • Virtex-5 LXT
  • More
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Less
IP
  • Endpoint Block Plus Wrapper for PCI Express
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
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