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AR# 34882

MIG Design Assistant - Virtex-6 Synthesis and Implementation Debug Guide

Description

This section of the MIG Design Assistant focuses on Synthesis and Implementation of the Virtex-6 DDR3/DDR2 designs. Below you will find information related to your specific question.
Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

For a complete list of Synthesis and Implementation debugging for Virtex-6 DDR3/DDR2 designs, please refer to the "Debugging Virtex-6 FPGA DDR2/DDR3 SDRAM Designs"=>"Synthesis and Implementation Debug" section of UG406:

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34285 MIG Design Assistant - Virtex-6 Synthesis and Implementation N/A N/A
AR# 34882
Date Created 05/19/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • MIG