We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome,
Internet Explorer 11,
Safari. Thank you!
AR# 34883: MIG Virtex-6 DDR2/DDR3 - Debugging issues with User Design simulations
MIG Virtex-6 DDR2/DDR3 - Debugging issues with User Design simulations
This section of the MIG Design Assistant focuses on simulation debug for a User Design simulation with Virtex-6 DDR3/DDR2 designs. Below you will find information related to your specific question.
Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
For a complete list of simulation debug steps for Virtex-6 DDR3/DDR2 designs please refer to the "Debugging Virtex-6 FPGA DDR2/DDR3 SDRAM Designs"=>"Simulation Debug"=>"Debug Issues with User Design Simulation" section of UG406:
Most user design simulation issues are related to incorrectly driving the User Interface. It's important to understand how to do so properly. For additional information on interfacing the core please refer to the"Interfacing to the Core"=>"Simulation Debug"=>"User Interface" section of UG406: