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AR# 34883

MIG Virtex-6 DDR2/DDR3 - Debugging issues with User Design simulations

Description

This section of the MIG Design Assistant focuses on simulation debug for a User Design simulation with Virtex-6 DDR3/DDR2 designs. Below you will find information related to your specific question.
Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

For a complete list of simulation debug steps for Virtex-6 DDR3/DDR2 designs please refer to the "Debugging Virtex-6 FPGA DDR2/DDR3 SDRAM Designs"=>"Simulation Debug"=>"Debug Issues with User Design Simulation" section of UG406:

Most user design simulation issues are related to incorrectly driving the User Interface. It's important to understand how to do so properly. For additional information on interfacing the core please refer to the"Interfacing to the Core"=>"Simulation Debug"=>"User Interface" section of UG406:

(Xilinx Answer 33698)- Driving User Interface

Linked Answer Records

Associated Answer Records

AR# 34883
Date Created 05/19/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • MIG